Semiconductor device

ABSTRACT

A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an MCP type semiconductor diskdevice capable of expanding memory and to a semiconductor device withprovisions to facilitate testing a plurality of chips accommodated in anMCP (Multi-Chip Package).

[0002] As demands are growing for higher integration density ofsemiconductor devices mounted on a printed circuit board, the packagesof semiconductor devices are getting smaller. In recent years, a varietyof kinds of CSPs (chip size packages), a general reference to packagesequal to or slightly larger than the chip size, have been developed.(The CSP package type is classified as a derivative of the existingpackages.) They are making large contributions to reducing size andweight of portable terminals.

[0003] At the same time, since the speed at which the memory capacityrequired by the system devices increases is higher than the speed atwhich the memory integration improves, a three-dimensional mounting of amemory has been proposed as a means to increase the memory capacitywhile minimizing an increase in the memory mounting area. The applicantof this invention developed a technology of DDP (Double Density Package)in which an LOC (Lead On Chip) structure is formed in layers to doublethe memory capacity of a package with the same external size as the1-mm-thick surface mount package TSOP (see JP-A-11-163255, laid open onJun. 18, 1999, corresponding to U.S. patent application Ser. No.09/161,725 filed on Sep. 29, 1998). This publication discloses a 128MDRAM-DDP, in which LOC structure (64MDRAM) lead frames are stacked inlayers and sealed with a mold, with the leads bonded.

[0004] Unlike a conventional magnetic disk device, a semiconductor diskdevice using a flash memory has no mechanical moving parts, and thus isunlikely to have erroneous operations and failures due to physicalimpacts. It has the advantages of being smaller in device size and ableto make a faster read/write access to data than in the conventionalmagnetic disk device. The semiconductor disk device has conventionallybeen realized as a memory board or memory card having a plurality offlash memories and a controller that controls the flash memories. Inthis case, the plurality of flash memories are realized as discrete LSIsand the controller is also realized as one LSI.

[0005] To deal with the aforementioned problem that a large number ofparts in the semiconductor disk device makes the size reductiondifficult, JP-A-6-250799, laid open on Sep. 9, 1994, discloses asemiconductor disk device in which a flash memory unit, an interfacewith external devices, and a controller unit are integrated in a singleLSI. The semiconductor disk device of a one-semiconductor-chipconfiguration has an expansion memory interface which, when the userwishes to expand the flash memory built into the chip, allows thestorage capacity of the semiconductor disk device to be increased, asrequired, by the user externally connecting a flash memory one chip at atime.

[0006] JP-A-11-86546, laid open on Mar. 30, 1999, discloses a technologywhereby a logic chip and a memory chip, fabricated separately, aremounted parallelly and sealed in one package. Further, JP-A-11-19370(corresponding to U.S. patent application Ser. No. 09/450,676, filed onNov. 30, 1999) shows an example structure of MCP.

SUMMARY OF THE INVENTION

[0007] The inventors of this invention studied a semiconductor diskdevice suited for incorporation into various portable informationterminals (palm size PC, handy terminal, etc.) and digital cameras asmain products to which the invention can be applied. The specificationsrequire the semiconductor disk device to have the smallest possiblemounting area, weight and power consumption. A controller is availablein a variety of kinds for various applications. For security reasons,the controller is expected to have its specification updated frequently,so that it is important to shorten the development period of new packageproducts to reduce cost—the common priority among the commercialproducts.

[0008] When a semiconductor disk device disclosed in JP-A-6-250799 is tobe manufactured in a single semiconductor chip configuration, i.e., inthe form of a system LSI, the following problems may arise: (1) there isa need to develop a new process, which in turn increases the number ofprocesses, leading to an increase in cost; (2) when all theconstitutional units are manufactured by the same process, theperformances of the individual units may become worse than when theindividual units are fabricated in the dedicated processes; (3)redesigning the entire chip as a result of changes in the specificationsof the controller unit is not advantageous in terms of reducing thedevelopment cost and shortening the development TAT; and (4) because theconstitutional units are arranged two-dimensionally, the size becomeslarge for a single chip.

[0009] In the LSI incorporated into a single package by arranging aplurality of chips parallelly as described in JP-A-11-86546, thereduction in the mounting area remains small to an extent that themounting area is not smaller than the sum of the areas of the individualchips.

[0010] (1) A first object of the present invention is to propose apackage configuration for the semiconductor disk device, which has asmall mounting area to facilitate its incorporation into small portableinformation terminals, and which can cope quickly with type changes ofthe controller due to specification changes, reduce the development TAT(Turn Around Time: time spent from the material processing to thedelivery of a product; or number of days from the start of developmentto the completion of development) and keep the development cost low.

[0011] Further, in a proposal to construct a semiconductor disk devicein the MCP configuration, the inventors of this invention studied theproblems experienced when conducting tests on a product incorporating amemory chip and a controller chip in a single package. The existingmemory and controller (logic) are individually packaged and subjected totests individually before being mounted on the printed circuit board.When combining two chips and forming them as a single package product,it is natural to conceive also bringing into the package the “wiring”that is on the printed circuit board between the memory and thecontroller. This, however, poses a problem in the testing that isconducted before shipping of the product. When the existing memory andcontroller are tested as individual single packages, the memory istested by a memory tester and the controller is tested by a logictester. These existing test environments, however, cannot be used underthe same conditions as in the conventional tests if the memory and thecontroller are incorporated into one package and internallyinterconnected as described above. When for example the memory is testedby the memory tester, the influence (leakage current) due to internallyconnecting the controller cannot be precluded entirely, so that theidentical test cannot be conducted under the conventional memory testingenvironment. The same can be said of the testing of the controller. Thatis, even if the influences of the internal connection is reduced as muchas possible and an analysis considering these influences is performed,the equality of the test is expected to deteriorate.

[0012] Further, the memory tester and the logic tester have differentcharacteristics. As the memory capacity increases, the test time alsoincreases. To deal with this situation the memory tester enhances thetest productivity by testing a large number of memories simultaneously.As for the logic tester, on the other hand, although it uses many signalterminals for applying a very large test pattern to the LSI beingtested, the test time is generally about two orders of magnitude smallerthan the memory test time. Because of this characteristic, the logictester enhances the test productivity by increasing the rate at whichthe LSIs are mounted and tested. If a mixed tester having both of thesetest functions with different characteristics is developed, the MCPpackages mounted on the mixed tester may be able to be subjected to bothof these test functions. However, there is a drawback that until thememory test is completed after the logic test has been finished, thelogic test terminals become idle without being utilized, eventuallydegrading the test productivity.

[0013] Hence, in view of the test productivity, i.e., efficientutilization of the expensive test system, it is considered promising totest the memory chip and the logic chip in the MCP two timesindividually. To realize this, it may be necessary to add to the memorytester and the test packages a function of isolating the influences dueto connecting the controller and to add to the logic tester and the testpackages a function of isolating the influences due to connecting thememory.

[0014] Therefore,

[0015] (2) it is the second object of this invention to propose an MCPmounting configuration which can efficiently utilize the expensive testsystem originally constructed to deal with individual separate chips ina conventional manner, keep low the cost and the number of processes forthe development of new test environments, and shorten the productdevelopment TAT.

[0016] (3) Further, it is checked whether the solution described above(2) that considers the efficiency of the development of test environmentcan be applied generally to a wide range of MCPs if the types of chipsto be combined, the functions to be incorporated, and the packageconfiguration should change.

[0017] (4) Further, it is also checked whether the present invention cansimilarly be applied to the system LSIs considering the problemsaccompanying the development of the test environment for a plurality ofLSI cores.

[0018] When the mounting configurations suited for the semiconductordisk device for incorporation into a variety of portable informationterminals and digital cameras are evaluated in terms of (1) smallmounting area and (2) low manufacturing cost, if the chip area is 40 mm²or greater, it is considered better to mount the memory chip and thecontroller chip in a stacked package (three-dimensional mounting) ratherthan integrating them into a one-chip system LSI (see NikkeiMicrodevices, August 1999, pp. 40-45). Hence, let us consider a casewhere a plurality of different kinds of chips (e.g., a combination of amemory chip and a controller chip) are three-dimensionally mounted inone package. Normally, these chips have different shapes and differentelectrode pad arrangements and thus the package configuration in thiscase differs from the one in which a plurality of chips of the sameshape and the same specifications are stacked as in the DDP and stackmemory. Among the package types currently in wide use, the following twotypes may be selected considering the ability to reduce themanufacturing cost by using the existing facilities and realize asignificant mounting area reduction effect.

[0019] (1) TQFP (Thin Quad Flat Package) type of four-directional leadarrangement structure in which a second semiconductor chip is stacked ona semiconductor chip of LOC (Lead On Chip) structure.

[0020] (2) Stacked chip CSP (Chip Size Package) type based on a smallBGA (Ball Grid Array).

[0021] The CSP type has a better mounting area reduction effect but, interms of the short development period for product design and the lowmanufacturing cost, the TQFP type using the low-cost lead frame issuperior.

[0022] Among the package configurations for the semiconductor diskdevice suited for incorporation into various portable informationterminals and digital cameras, the first proposed solution is a TQFPtype which has a short development period for product design achieved bycombining the existing chips and packaging them and which has the lowestmanufacturing cost realized by stacking a plurality of chips on a singlelead frame. The TQFP type will be disclosed in the first embodiment. Asfor the expansion of the memory in the semiconductor disk device, thepackage is provided with a memory expansion terminal. This embodimenthas specifications that allow the controller to access the externallyconnected expansion memory in the same way as accessing the built-inmemory.

[0023] Facilitating the testing of a plurality of chips incorporated inthe MCP, which is the second object of the present invention, isproposed as follows.

[0024] In the embodiment 1, the controller and the flash memory in thepackage constituting the semiconductor disk device are basically notinternally connected. The electrode pads of the controller chip and theflash memory chip are independently connected to the external terminals.The power supply or ground may be connected to a common externalterminal of the two chips. When the semiconductor disk device describedabove is in use, it is mounted on the board and its external terminalsare interconnected by wires on the board. The controller accesses theflash memory via the external terminals and the wires on the board.

[0025] With this arrangement, the flash memory and the controller in thepackage of this invention, when viewed from outside the package, operateindependently of each other through the external terminals. Hence, bymounting the packages of this invention in the test environment that wasoriginally developed for testing the conventional discrete chips, thememory test and logic test can be executed successively in the same wayas with the individual discrete chips. With the method of thisinvention, reliable tests identical with the conventional ones can beperformed without adding to the memory and logic test environments afunction of isolating the influences of other chips.

[0026] The MCP configuration of this invention that enables independenttests is not limited to the MCP of the embodiment 1 having a combinationof the flash memory and the controller (ASIC) but can be applied, withthe similar effects, to any MCPs in any form of package with any numberof combined chips.

[0027] As a variation of this invention, it is possible to provide aselector on the internal wires between a plurality of chips in the MCPand to supply a test mode signal from the external terminal to theselector to select between two modes, a mode in which the plurality ofchips are disconnected from each other and can be independently testedfrom the external terminals and a mode in which the plurality of chipsare internally interconnected to allow inter-chip accesses inside thepackage. In this case, a selector with a function of connectionswitching according to the mode signal is installed on the internalwires in the package or in the controller chip.

[0028] A package is provided which incorporates into a flash memory asystem program conforming to the combination of a flash memory and acontroller and which guarantees that the system program operatesnormally.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a block diagram of a semiconductor disk device accordingto an embodiment of this invention.

[0030]FIG. 2 is a plan view of the semiconductor disk device accordingto an embodiment of this invention with the top portion of a resinsealing body removed.

[0031]FIG. 3 is a schematic cross section taken along the line A-A ofFIG. 2.

[0032]FIG. 4 is a schematic cross section taken along the line B-B ofFIG. 2.

[0033]FIG. 5 is a schematic cross section taken along the line C-C ofFIG. 2.

[0034]FIG. 6 is an example arrangement of signals allocated to theexternal terminals of the semiconductor package of the semiconductordisk device according to an embodiment of the invention.

[0035]FIG. 7 is an example of connections when the semiconductor diskdevice according to an embodiment of this invention is mounted on aboard.

[0036]FIG. 8 is a block diagram of a controller provided in thesemiconductor disk device according to embodiment 1 of this invention.

[0037]FIG. 9 is a block diagram of a flash memory provided in thesemiconductor disk device according to embodiment 1 of this invention.

[0038]FIG. 10 is a memory map of a 64-Mb flash memory provided in thesemiconductor disk device according to embodiment 1 of this invention.

[0039]FIG. 11 is an example of connecting an expansion memory to thesemiconductor disk device according to embodiment 1 of this invention.

[0040]FIG. 12 is an example of signal allocation to the externalterminals considering the ease with which to connect a semiconductordisk device on the board according to embodiment 2 of this invention.

[0041]FIG. 13 is a cross section of a stack type CSP embodying thisinvention.

[0042]FIG. 14 is an example of connecting signals to the externalterminals of the CSP of FIG. 13.

[0043]FIG. 15 is an example of connecting the external terminals of theCSP of FIG. 13 on the board.

[0044]FIG. 16a is an example of a lead frame type MCM embodying thisinvention.

[0045]FIG. 16b is another example of a lead frame type MCM embodyingthis invention.

[0046]FIG. 16c is still another example of a lead frame type MCMembodying this invention.

[0047]FIG. 17 is a diagram showing how independent terminals of aplurality of chips are integrated into one package.

[0048]FIG. 18 is a diagram showing how the controller and the DRAM areincorporated into one package.

[0049]FIG. 19 is a diagram showing how the DRAM and the flash memory areincorporated into one package.

[0050]FIG. 20 is an example cross section of a memory cell in the flashmemory.

[0051]FIG. 21 is a block diagram of a semiconductor disk device with abuilt-in test selector.

[0052]FIG. 22 is a block diagram of a semiconductor disk deviceincorporating a test selector in the controller chip.

[0053]FIG. 23 is an embodiment in which an MCP has expansion terminalsfor expansion memories.

[0054]FIG. 24 is a block diagram showing a semiconductor disk device ofthis invention used as a system LSI.

[0055]FIG. 25 is an example of a stacked type package of expansionmemory.

DESCRIPTION OF THE EMBODIMENTS

[0056] Now, embodiments of this invention will be described in detail byreferring to the accompanying drawings. Throughout all the drawingsshowing example embodiments of the invention, components havingidentical functions are assigned like reference numerals and theirrepetitive explanations are omitted.

[0057] (Embodiment 1)

[0058]FIG. 1 shows a block diagram of a semiconductor disk device 100constructed of a single semiconductor package 10 according to thepresent invention. A memory chip 20 and a controller chip 30, bothmaking up the semiconductor disk device 100, are not internallyconnected in the semiconductor package 10 but their signal terminals (aplurality of electrode pads are hereinafter generally called “electrodepads 21, 22, 31-34”) are independently and internally connected toexternal terminal blocks 11-16 (each external terminal block consists ofa plurality of external terminals and these external terminal blocks arehereinafter generally called “external terminals”). That is, thecontroller chip 30 has an electrode pad 31 for transferringaddress/various access signals to and from an external host unit and anelectrode pad 32 for transferring data/command signals to/from theexternal host unit. These electrode pads 31, 32 are internally connectedby 317, 318 to an external terminal 11 (host interface) for connectionwith the host unit of the semiconductor package 10 to outputaddress/data/command signals to the memory. The controller chip 30 alsohas an electrode pad 33 for inputting data signals from the memory andan electrode pad 34 for inputting and outputting memory access controlsignals. The electrode pad 33 is internally connected to an externalterminal 12 (memory interface) of the semiconductor package 10 and theelectrode pad 34 is internally connected to external terminals 13, 16for access control signals of the semiconductor package 10. As to thememory chip 20, an electrode pad 21 for inputting address/data/commandsignals from the controller chip 30 and outputting data signals to thecontroller chip 30 is internally connected to an external terminal 14 ofthe semiconductor package 10; and an electrode pad 22 for inputting andoutputting access control signals to and from the controller isinternally connected to an external terminal 15 that handles accesscontrol signals of the semiconductor package 10. As to other signals,power supply (Vcc) and ground (Vss), for the input/output of which thecontroller chip 30 and the memory chip 20 are required to connect toexternal circuits outside the semiconductor package 10, other electrodepads of the controller chip 30 and memory chip 20 are internallyconnected to other external terminals of the semiconductor package 10.In that case, the electrode pads for the ground (Vss) and power supply(Vcc) may be connected to common external terminals or a part of thesignals may be connected to common external terminals. Or they may beinternally connected.

[0059] The semiconductor package 10 according to an embodiment of thisinvention is mounted on a mother board 150, and the external terminal 12(memory interface) and the external terminal 14 of the semiconductorpackage 10 are externally connected by a memory bus 301 on the board.Similarly, the external terminal 13 and the external terminal 15 of thesemiconductor package 10 are externally connected by a control bus 302on the board 150. With the controller chip 30 and the memory chip 20interconnected in this way, the access control of the semiconductor diskdevice can made.

[0060] By avoiding the internal connection between the controller chip30 and the memory chip 20 in the semiconductor package 10 as much aspossible, a test on individual chips using a test system through theexternal terminals can be performed while minimizing influences fromother chips. This enhances the reliability of the test.

[0061] Further, to enable an expansion of the memory capacity, thesemiconductor disk device 100 according to an embodiment of thisinvention is provided with a memory expansion terminal 16, to which anexpansion memory 50 can be externally connected so as to be accessed bythe controller chip 30. The memory expansion is realized by connectingthe expansion memory 50 mounted on the mother board 150 to the memorybus 301 and the control bus 302—which interconnect the controller chip30 and the memory chip 20—in the same hierarchy (a form of connectionthat supplies the address and various control signals commonly). A partof an access control signal 303 is not only transferred between thecontroller chip 30 and the built-in memory chip 20 but also to theexpansion memory 50. An access control signal 304 dedicated for theexpansion memory is directly transferred from the controller chip 30through the memory expansion terminal 16 to the expansion memory 50.Which of the built-in memory 20 and the expansion memory 50 is to beaccessed is determined by which of chip enable signals F_CEA_1-F_CEA_5described later is generated. The expansion memory 50 may be mounted asa package which contains one or more memory chips, each having the samespecification as or different capacity from the built-in memory 20.

[0062]FIG. 2 shows an example of the semiconductor disk device 100according to an embodiment of this invention formed in a singlesemiconductor package 10. FIG. 2 is a plan view of TQFP (Thin Quad FlatPackage) type semiconductor package 10 of a 4-way lead array structurewith the top portion of a resin sealing body removed. FIG. 3 is aschematic cross section taken along the line A-A of FIG. 2. FIG. 4 is aschematic cross section taken along the line B-B of FIG. 2. FIG. 5 is aschematic cross section taken along the line C-C of FIG. 2.

[0063] As shown in FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the semiconductordisk device 100 of the embodiment 1 has: a controller chip 30 having aplurality of electrode pads 4 formed on a principal surface 30X of asquare semiconductor substrate; a memory chip 20 having a plurality ofelectrode pads 4 formed on a principal surface 20X of a squaresemiconductor substrate larger than the semiconductor substrate of thecontroller chip 30; a plurality of leads 7 arranged around the outerperipheries of the controller chip 30 and the memory chip 20, the leads7 each consisting of an inner portion 7A and an outer portion 7B, theinner portions 7A being electrically connected to the electrode pads 4of the controller chip 30 and memory chip 20 through conductive wires 8;a support lead 6 for supporting the memory chip 20; and a resin sealingbody 9 sealing the controller chip 30, memory chip 20, wires 8 and innerportions 7A of the leads 7.

[0064] The support lead 6 has suspension lead portions 6A and asemiconductor chip support lead portion (bus bar) 6B integrally formed,the suspension lead portions 6A being arranged between lead groups eachconsisting of a plurality of the leads 7, the semiconductor chip supportlead portion 6B being arranged in a central space portion enclosed bythe front ends of the inner portions 7A of the leads 7. A lead framemade up of the leads 7 and the support lead 6 may be manufactured byetching or pressing a flat plate material made of ion (Fe)-nickel (Ni)alloy or copper (Cu) or Cu-based alloy to form a predetermined leadpattern.

[0065] The controller chip 30 is mounted on the principal surface (topsurface) 20X of the memory chip 20, and the bottom surface of thecontroller chip 30 opposite the principal surface 30X is bonded to theprincipal surface 20X of the memory chip 20 with an adhesive 5 to form asemiconductor chip stacked structure. The principal surface 20X of thememory chip 20 of the semiconductor chip stacked structure is securelybonded with the semiconductor chip support lead portion 6B to supportthe semiconductor chip stacked structure. The top surface of thesemiconductor chip support lead portion 6B is lower than the peak of thewires 8.

[0066] The resin sealing body 9 is formed square in plan view. In theembodiment 1, for example, it is shaped rectangular. Along the foursides of the resin sealing body 9 are arranged a plurality of outerportions 7B of the leads. The outer portions 7B of the leads are shapedlike a gull wing for surface mounting.

[0067] The semiconductor package 10 can be reduced in thickness becausethere are no tabs between the principal surface 30X of the controllerchip 30 and the principal surface (top surface) 20X of the memory chip20. By securely bonding the semiconductor chip support lead portion 6Bto the principal surface 20X of the memory chip 20, the thickness of thesupport lead 6 can be canceled by the loop height of the wires 8. Thus,the support lead 6 has no adverse effect on the thickness of the resinsealing body 9. As a result, it is possible to reduce the thickness ofthe semiconductor package 10 having a plurality of chips arranged inlayers and to construct the package in the form of the TSOP.

[0068] In this embodiment, the area of the memory chip 20 is larger thanthe area of the controller chip 30. In such a case, because the chipwith a larger area has a weaker bending strength, it is advised to makethe chip with a larger area thicker than the other rather than settingthe thicknesses of the two chips equal.

[0069] To construct the above-described stack type MCP in the form ofTSOP, it is necessary to distribute a total number of electrode pads ofa plurality of chips among different directions according to the leadnumber ratio among the four sides in order to avoid crossing or nearingof the wires when the electrode pads 4 of each chip are connected by thewires 8 to the inner portions 7A of the leads 7 arranged at the foursides. In the example shown in FIG. 2, the arrangement density of theelectrode pads at one side of the controller chip 30 is made coarserthan those at other three sides and the electrode pads of the memorychip 20 are collectively arranged at one side corresponding to thatcoarse density side of the controller chip 30. Combining these two chipsmakes the overall ratio in the number of electrode pads among the foursides almost equal to the lead number ratio, thus eliminating thecrossing of the connection wires.

[0070]FIG. 6 shows an example arrangement of signals for those externalterminals (outer portions 7B of the leads) of the semiconductor package10 of FIG. 2 which are wire-bonded as described above, with terminalnames indicated. For example, a VCC terminal is a controller powerpotential terminal with 3.3 volts (V) or 5 volts (V) for example. A VCCfterminal is a memory power potential terminal with 3.3 volts (V) forinstance. A VSS terminal is a reference potential terminal fixed at areference potential (0 V for example). I/O0 to I/O7 terminals areconnected to an electrode pad 21 of the memory chip 20 to input andoutput an address/data/command to and from the memory. F_DA(0) toF_DA(7) terminals are connected to an electrode pad 33 of the controllerchip 30 to input and output an address/data/command to and from thememory. F_CEA_1 to F_CEA_5 terminals are used as follows. When thecontroller selects the memory 20 in the package, it selects the F_CEA_1terminal to output a chip enable signal 1; and when the controllerselects the external expansion memory 50, it selects the F_CEA_2 toF_CEA_5 terminals to output chip enable signals 2-5 to the expansionmemory. F_OEA terminal is set by the controller when reading data fromthe memory. F_RDY_1 and F_RDY_2 terminals are set by the controller toperform write and erase operations on the memory. F_WEA terminal is setby the controller to output a memory write enable signal. F_SC_A1 andF_SC_A2 terminals are set with a serial clock by the controller. F_CDEAterminal is set by the controller to control a multiplex bus whenwriting into the memory. F_RES terminal is set with a RESET signal bythe controller. Table 1 shows functions assigned to external terminals.TABLE 1 Terminal Terminal Function # name Function # name 1 Vss Ground51 H_D(5) Data 5 2 Vcc Power supply 52 H_D(6) Data 6 3 Vccf Power supply53 H_D(11) Data 11 (flash) 4 /RES Reset 54 HD(12) Data 12 5 RDY//BusyReady/busy 55 HD(13) Data 13 6 /CDE Command data enable 56 Vss Ground 7/OE Output enable 57 HD(14) Data 14 8 Vss Ground 58 HD(7) Data 7 9 I/O0Input/output 0 59 H_CE1 Chip enable 1 10 I/O1 Input/output 1 60 HA(1O)Address 10 11 F_RDY_2 Ready (for 61 H_OE output bank 2) enable 12 I/O2Input/output 2 62 HD(15) Data 15 13 F_RES Reset 63 H_CE2 Chip enable 214 I/O3 Input/output 3 64 H_IORD Read data control 15 TEST1 Diagnostic65 H_IOWR Write data control mode selection 16 Vcc Power supply 66 VccPower supply 17 Vccf Power supply 67 H_A(9) Address 9 (flash) 18 I/O4Input/output 4 68 H_A(8) Address 8 19 I/O5 Input/output 5 69 H_A(7)Address 7 20 I/O6 Input/output 6 70 H_A(6) Address 6 21 I/O7Input/output 7 71 Vss Ground 22 F_CEA_1 Chip enable 1 72 H_WE Writeenable 23 F_CEA_2 Chip enable 2 73 H_IREQ Interrupt request 24 Vcc Powersupply 74 CSEL Card select 25 SC Serial clock 75 TEST2 Diagnostic input1 mode selection 2 26 F_SC_A1 Serial clock 76 H_RESET Reset output 1 27/WE Write enable 77 WAIT Wait 28 /CE Chip enable 78 H_A(5) Address 5 29Vss Ground 79 H_A(4) Address 4 30 F_SC_A2 Serial clock 80 H_A(3) Address3 output 2 31 Vss Ground 81 H_A(2) Address 2 32 F_CEA_3 Chip enable 3 82H_INPACK Input acknowledge 33 F_CEA_4 Chip enable 4 83 H_REG Register 34F_CEA_5 Chip enable 5 84 DASP Handshake control 35 F_WEA Write enable 85H_STSCHG Status signal 36 FDA(7) Data 7 86 H_A(1) Address 1 37 FDA(6)Data 6 87 H_A(0) Address 0 38 FDA(S) Data 5 88 H_D(0) Data 0 39 VccPower supply 89 H_D(1) Data 1 40 F_DA(4) Data 4 90 H_D(2) Data 2 41F_DA(3) Data 3 91 H_I0IS16 16-bit assert signal 42 F_DA(2) Data 2 92H_D(8) Data 8 43 F_DA(1) Data 1 93 H_D(9) Data 9 44 F_DA(0) Data 0 94H_D(10) Data 10 45 F_OEA Output enable 95 Vcc Power supply 46 F_CDEACommand data 96 PORST Port enable 47 F_RDY_1 Ready signal 1 97 TEST3Diagnostic mode selection 3 48 Vcc Power supply 98 TEST4 Diagnostic modeselection 4 49 H_D(3) Data 3 99 XIN Quartz oscillation (IN) 50 H_D(4)Data 4 100 XOUT Quartz oscillation (OUT)

[0071]FIG. 7 shows example combinations of external terminals that theuser is required to short-circuit with wires on the board (by connectingtwo points in the circuit at different potentials using a conductor witha very low resistance) and an example of wiring on the board when thesemiconductor package 10 of the embodiment 1 having signals assigned toits external terminals as shown in FIG. 6 is mounted on the board. Forexample, the F_DA(0) terminal of pin number 44 internally connected tothe controller and the I/O0 terminal of pin number 9 internallyconnected to the memory are externally connected together. The F_RDY_1terminal of pin number 47 internally connected to the controller and theRDY/Busy terminal of pin number 5 internally connected to the memory areexternally connected together. By externally connecting other terminalsaccording to the combinations shown in FIG. 7, the semiconductor device100 of this invention is made to function as a semiconductor diskdevice. If the external connecting wires on the board are arranged asshown in FIG. 7 without any crossing, short-circuit connections can bemade on a single wiring layer on the board. This arrangement cansuppress an increase in the number of wiring layers on the board andminimize the degree to which these wires are hindrance to other wires.The signal allocation to the external terminals arranged in such amanner as to minimize the crossing of the wires on the board asdescribed above is considered necessary.

[0072]FIG. 8 shows an example block diagram of the controller 30 andFIG. 9 shows an example block diagram of the flash memory 20.

[0073] The function of the controller shown in FIG. 8 has an interfacethat conforms to the specifications defined by PCMCIA (Personal ComputerMemory Card International Association) and supports all operation modesincluding a memory card mode, an I/O card mode and an IDE (IntegratedDevice Electronics) compatible mode. The controller allows the host unitto access the memory according to a method similar to that of the memorycard or I/O card (PC card) or through an interface similar to that ofthe conventional IDE compatible hard disk drive. This controller, asshown in the figure, comprises a 16-bit CPU as a core processor 38, ahost interface control unit 35, a data transfer control unit 36, and amemory interface control unit 37.

[0074] The host interface control unit 35 has a register for recordingvarious property information on hardware resource or CIS (CardInformation Structure) referenced by the host unit in the PC card accessmode and a CCR (Card Configuration Register) storing various cardstandard specifications. When the host unit accesses the semiconductordisk device 100, the host unit sends a command compatible, for example,with the ATA specification (AT Attachment: the specificationstandardized by ANSI (American National Standard Institute) based on theIDE, one of hard disk drive interfaces) via a host unit connectionexternal terminal (host interface) 11 and references the CIS toestablish the connection and then execute the reading and writing ofdata. The host interface control unit 35 receives the command, decodesit and temporarily stores in a task register an address representing anaccess start position, a data length and write data supplied. When thedata is to be read out, the host interface control unit 35 temporarilyaccumulates the data read from the memory in the task register and sendsthe data to the host unit in response to an ATA-compatible command.

[0075] The memory interface control unit 37 forms an interface accordingto the unique characteristic of the memory built into the semiconductordisk device 100 or of the expansion memory. By using a memory commanddedicated to the memory, the memory interface control unit 37 performsthe memory access control. When the memory specification changes, onlythe specification of the memory interface control unit 37 needs to bechanged. The memory interface control unit 37 checks whether the addressaccessed by the host unit corresponds to the built-in (flash) memory orthe external expansion (flash) memory, and generates a chip enablesignal for the associated (flash) memory. At the same time, theATA-compatible command from the host unit is converted into a memorycommand which is then fed to the associated (flash) memory via theexternal terminal 12 (memory interface). Upon receiving the chip enablesignal, the (flash) memory enters an active state and its operation modefor access control is set by the memory command from the memoryinterface control unit 37.

[0076] <Overall Configuration of Flash Memory>

[0077]FIG. 9 shows an overall configuration of the flash memory 20 to beaccess-controlled by the memory interface control unit 37.

[0078] The memory matrix (memory array) 201 has a large number ofelectrically erasable and programmable, nonvolatile memory celltransistors arranged in arrays. The memory cell transistors each have,as shown in FIG. 20, a source S and a drain D formed in a semiconductorsubstrate or a memory well SUB, a floating gate FG formed in a channelregion with a tunnel oxide layer interposed between it and the memorywell, and a control gate CG formed over the floating gate with aninterlayer insulating layer therebetween. The control gate CG isconnected to a word line 221, the drain D to a bit line 220, and thesource S to a source line not shown.

[0079] The external input/output terminals I/O0-I/O7 serve as addressinput terminals, data input terminals, data output terminals and commandinput terminals. The X-address signal (sector address signal) input fromthe external input/output terminals I/O0-I/O7 is supplied through amultiplexer 202 to an X-address buffer 203. An X-address decoder 204decodes an internal complementary address signal output from theX-address buffer 203 to drive the word line 221.

[0080] (At one end of the bit lines 220 a sense latch circuit not shownis provided; and at the other end a data latch circuit not shown isprovided.) The bit line 220 is selected by a Y-gate array circuit 207based on a selection signal output from a Y-address decoder 206. AY-address signal input from the external input/output terminalsI/O0-I/O7 is preset in a Y-address counter 205 where the address signalis incremented from a preset value as a starting point and is given tothe Y-address decoder 206. The bit line 220 selected by the Y-gate arraycircuit 207 is connected to an input terminal of an output buffer 208during the data output operation and, during the data input operation,to an output terminal of an input buffer 210 through a data controlcircuit 209. The bit lines 220 are provided with a data register 215that holds one sector of write data. The write data is taken in 8 bitsat a time from the external input/output terminals I/O0-I/O7 and storedin the data register 215. When one sector of write data is stored in thedata register 215, the write data is written into a sector addressspecified by the X-address.

[0081] The connections between the output buffer 208, the input buffer210 and the external input/output terminals I/O0-I/O7 are controlled bythe multiplexer 202. A command supplied from the external input/outputterminals I/O0-I/O7 is given to a mode control circuit 211 through themultiplexer 202 and the input buffer 210. The data control circuit 209processes logic data representing the control of the mode controlcircuit 211 as well as the data supplied from the external input/outputterminals I/O0-I/O7 so that they can be fed into the memory array 201.

[0082] A control signal buffer circuit 212 is supplied with accesscontrol signals, i.e., a chip enable signal CE, an output enable signalOE, a write enable signal WE, a serial clock signal SC, a reset signalRES, and a command enable signal CDE. The mode control circuit 211controls an external signal interface function according these accesscontrol signals and also controls an internal operation according to thecommand code. When inputting a command or data from the externalinput/output terminals I/O0-I/O7, the command enable signal CDE isasserted. If a command is input, the write enable signal WE is alsoasserted; and if data is input, the write enable signal WE is negated.If an address is input, the command enable signal CDE is negated and thewrite enable signal WE is asserted. Thus, the mode control circuit 211can distinguish between the command, data and address that are inputfrom the external input/output terminals I/O0-I/O7 through multiplexer.The mode control circuit 211 can notify its state to the externalcircuit by asserting a Ready/Busy signal RDY/Busy during the erase orwrite operation.

[0083] An internal power supply circuit 213 generates a variety ofoperation power supplies 222 for writing, erase verification and readingand feeds them to the X-address decoder 204 and memory cell array 201.

[0084] The mode control circuit 211 performs an overall control on theflash memory 20 according to the memory command. The operation of theflash memory 20 is determined basically by the memory command. Thememory commands assigned to the flash memory 20, as shown in Table 2,include such commands as read, erase, additional write, rewrite, eraseverify, reset and status register read/clear. TABLE 2 First bus cycleSecond bus cycle Third bus cycle Fourth bus cycle Bus Operation DataOperation Data Operation Data Operation Data Command cycles mode in modein/out mode in mode in Read 3 Write 00H Write SA(1) Write SA(2) Erase 4Write 20H Write SA(1) Write SA(2) Write B0H (Single sector) Erase 4Write  7FH Write BA(1) Write BA(2) Write B0H (Block) Additional 4 Write10H Write SA(1) Write SA(2) Write 40H write Rewrite 4 Write  1FH WriteSA(1) Write SA(2) Write 40H (Pre-erase) Additional 4 Write  0FH WriteSA(1) Write SA(2) Write 40H write (Control bytes) Erase verify 4 WriteAOH Write SA(1) Write SA(2) Write A0H Reset 1 Write FFH Status 2 Write70H Read SRD register Read Status 1 Write 50H register Clear

[0085] The flash memory 20 has a status register 214 to indicate itsinternal state. The content of the status register 214 can be read outfrom the external input/output terminals I/O0-I/O7 by asserting thesignal OE. For example, according to the additional write command, themode control circuit 211 performs the data write control and verifiesthe result of the write operation. When the write operation results inan error, the write operation is attempted a predetermined number oftimes. If the error still persists, a write abnormal flag is set in thestatus register 214. The controller can check if the data writeoperation is normally ended by issuing a status register read commandafter it has issued an additional write command.

[0086] The memory interface control unit 37 in FIG. 8 has a definitionof correspondence relation between disk addresses representing accessstart positions specified by the host unit (track number, sector number,etc.) and memory addresses of the (flash) memory (block number, sectornumber, chip number, etc.) and references it to convert a disk addressspecified by the host unit into a corresponding memory address of the(flash) memory. For example, FIG. 10 shows a memory map of a 64-Mbitflash memory, with each sector comprising 512 data bytes and 16 controlbytes. The memory interface control unit 37 controls a sequentialread/write access to this memory one sector at a time. During the datawrite mode, the memory interface control unit 37 extracts the write dataaccumulated in a data buffer 39 512 bytes at a time and transfers themto the flash memory 8 bits at a time through the external terminal 12and memory bus 301. During the read mode, the memory interface controlunit 37 transfers read data 8 bits at a time from the flash memory intothe data buffer 39. The internal state read from the status register 214of the flash memory 20 is written into the Control/status register. Theread data that was normally read and stored in the data buffer 39 istransferred by the host interface control unit 35 to the host unitthrough the host interface 11. At the same time, processing to checkthat the data has been normally written is also performed by reading thedata written into the flash memory 20 in the write mode and checking itagainst the write data. For the read/write control on the flash memory20, the memory commands (Table 2) and the access control signals areissued. The memory interface control unit 37 multiplexes the memorycommand, address and data and transfers them through the memoryinterface 12.

[0087] The control bytes, redundant bytes added to each of the sectorsshown in FIG. 10, are written with information including an errorcorrecting code (ECC) for the data region of the associated sector, anidentification code representing writable region/replacement region/badregion, a logic address, and a number of rewriting operations. Eachsector is checked at an initial stage or at any arbitrary time to seewhether the storage operation can be made or not. The sectors thatfailed the check are attached with the “bad regions” identification codefor management. In the flash memory shown in FIG. 10, it is guaranteedthat there are at least 16,057 good sectors (sectors that can be used aswritable region/replacement region). Memory cells in the data regionwhere a write error has occurred are replaced with the memory cells ofcontrol bytes.

[0088] The data transfer control unit 36 of FIG. 8 stores the write datasent from the host unit into the data buffer 39, then generates an errorcorrecting code ECC based on the BCH code (Bose-Chaudhuri-Hocquenghemcode) theory and writes it into the control bytes. The memory interfacecontrol unit 37 writes the write data stored in the data buffer 39 andthe error correcting code ECC into the memory. The data transfer controlunit 36 stores the read data read out from the memory into the databuffer 39 and, based on the error correcting code ECC in the controlbytes that was read out at the same time, performs error correctionprocessing on the read data. The error correcting processing corrects upto two bits of errors in the 512 bytes of data per sector, for example.

[0089] When a security is required of the information to be stored inthe memory, a variety of encryption processing is executed. The datatransfer control unit 36 encrypts the write data held in the data buffer39 and decrypts the read data. Possible encryptions for use include“MULTI2” and American DES (Data Encryption Standard) in the “common keyencryption” system and RSA encryption in the “public key encryption”system. It is also conceivable to encrypt the read data to be sent outto the host unit and decrypt the data received from the host unit.

[0090] As described above, because the controller chip 30 of FIG. 8 isdivided into function blocks, it is possible to deal with a change inthe host unit interface specification by changing the function of onlythe host interface control unit 35. When the memory specification ischanged, this can be dealt with similarly by changing the function ofonly the memory interface control unit 37.

[0091]FIG. 11 shows an example of connections for expanding the (flash)memory in the embodiment where the semiconductor disk device 100 of thisinvention shown in FIG. 7 is mounted on the board. The I/O0-I/O7terminals of the expansion (flash) memory 50 are connected, outside thesemiconductor disk device 100 (on the board), to the F_DA(0)-F_DA(7)terminals of the controller, as with the I/O0-I/O7 terminals of thebuilt-in (flash) memory. The built-in (flash) memory and the expansion(flash) memory are connected on the memory bus in the same hierarchy (aform of connection that supplies the address, data and various controlsignals commonly). As to other access control signals, the followingconnections are made. For the chip enable signal CE, the outputterminals F_CEA_1, F_CEA_2 of the controller are connected to thebuilt-in (flash) memory and the expansion (flash) memory respectively.Similarly, for the serial clock signal SC, the F_SC_A1, F_SC_A2terminals of the controller are connected to the memories respectively.For the ready/busy signal RDY/Busy, the F_RDY_1, F_RDY_2 terminals ofthe controller are likewise connected to the memories respectively. Forthe command enable signal CDE, output enable signal OE and write enablesignal WE, the signal terminals of the controller are commonly connectedto the signal terminals of the built-in (flash) memory and the expansion(flash) memory.

[0092] Thus, the memory expansion terminal for the expansion (flash)memory (external terminal 16 of FIG. 1) generally refers to the externalterminals for the chip enable signal CE, serial clock signal SC andready/busy signal RDY/Busy.

[0093] The expansion (flash) memory 50 is mounted on the board in theform of a package three-dimensionally incorporating a plurality ofmemory chips, as shown in FIG. 25. As the required memory capacityincreases, this mounting configuration is considered a promising one.Semiconductor chips 51, 52 are constructed of, for example, 64-Mbitflash memories EEPROM (Electrically Erasable & Programmable Read OnlyMemory). The semiconductor chips 51, 52 are securely bonded togetherwith an adhesive layer 5 therebetween and with their back surfaces incontact, and are shifted from each other in a direction perpendicular tothe arrangement direction of the electrode pads 4. The semiconductorchips 51, 52 are each supported by the support lead portion 6B, and theelectrode pads 4 and leads 7 are each electrically connected throughwires 8. These are wholly sealed by the resin sealing body 9.

[0094] Where the expansion memory 50 of FIG. 11 has a multichipstructure as described above, the component expansion memories 51, 52are commonly connected to the bus interconnecting the controller chip 30and the built-in memory 20, except that the access control signalsdedicated to the memory chips (chip enable signal CE, serial clocksignal SC and ready/busy signal RDY/Busy) are connected individually toeach of the expansion memories 51, 52. The semiconductor disk devicewith an expansion memory mounted on the mother board is constructed inthis way.

[0095] The semiconductor disk device 100 according to embodiments of thepresent invention described above incorporates a plurality of differentkinds of semiconductor chips in a single package and thus the testsconducted on these chips differ because the chips are of differentkinds. It is therefore necessary to conduct different tests on thedifferent semiconductor chips after the package has been assembled. Toenhance the precision at which to identify faulty locations requirespreventing a leakage current produced by one semiconductor chip fromentering the input and output terminals of the other semiconductor chip.As a solution to this requirement, it is conceivable to avoid as much aspossible the internal connection between the plural chips in thesemiconductor disk device 100 and extract their leads independently ofeach other to the external terminals of the package. Only the ground Vssmay be commonly shared. The chips are each provided with an independentpower supply Vcc terminal to enhance the accuracy of the standby currentscreening test.

[0096] The testing of the semiconductor disk device 100 may beefficiently conducted in two steps: one for checking a plurality ofmemory chips simultaneously by a memory test system and one for checkingthe controller at high speed by a logic test system. This offers a greatadvantage of being able to utilize the test environments of theindividual semiconductor chips and reduce a turnaround time (TAT) forthe semiconductor device development.

[0097] (Embodiment 2)

[0098]FIG. 12 shows an example of external terminal arrangement,different from the one shown in FIG. 6, that considers facilitating theexternal short-circuiting connections outside the semiconductor diskdevice 100. What is changed from FIG. 6 is that the terminals requiredto be externally connected are arranged adjacent to each other to apractically feasible extent to reduce an external connection distancebetween the external terminals from the controller chip 30 and theexternal terminals from the memory chip 20.

[0099] In the embodiment 1 shown in FIG. 6, the existing controller chipand memory chip are mounted in one package and the electrode padarrangements of the controller chip and the memory chip are originallydetermined mainly for their own separate packages. Even when theseexisting chips are used, the example configuration shown allows theexternal terminals to be arranged at four sides by connecting theelectrode pads to the leads through wires as shown in FIG. 2 if somechanges or improvements are made as to the horizontal positionalrelationship among a plurality of stacked chips, the arrangement of theelectrode pads and the wire connection positions. It is also necessary,however, to consider a burden on the part of the user connecting theexternal terminals through wiring on the board.

[0100] The embodiment 2 shown in FIG. 12 can be realized, for example,by designing the arrangement of the electrode pads of the controller tosuit the MCP application so that the external terminals of thecontroller chip and memory chip that are required to be connected can beplaced adjacent to each other. If the external terminals to be connectedtogether are placed close to each other, the user can easily makeshort-circuit connections on the board. Because of various restrictionsimposed on the arrangement of the electrode pads on the chip, it is onlyto a practically feasible extent that the proximate placement of theexternal terminals to be connected is considered achievable.

[0101] (Embodiment 3)

[0102]FIG. 13 shows an example cross section of a stacked CSPimplementing the present invention. Like the embodiment 1, thisembodiment has the controller chip 30 and the memory chip 20accommodated in a single package. The electrode pads of each chip areconnected to electrode portions of an interconnect layer 112 throughwires 114, and external terminals 115 are formed and connected to landportions 117 of the interconnect layer 112 through via holes 116 in aninsulating substrate 111. The interconnect layer 112 is formed often inmultiple layers rather than in a single layer.

[0103] This embodiment, too, as in the embodiment 1, basically does notinternally connect the input/output terminals of the controller chip 30and memory chip 20 for the address, data, command and access controlsignals but connects them independently to the external terminals 115.Other signals and power supplies are also connected basicallyindependently to the external terminals 115.

[0104]FIG. 14 is a conceptual diagram showing an example of internalconnections in the CSP and in the interconnect layer of those signalswhich are required to be externally connected to the external terminals115 of the CSP of FIG. 13. Signal names are identical with those shownin FIG. 6. The reason for making connections to the external terminals115 in a manner shown in FIG. 14 is that when the CSP is mounted on theboard, the on-board wiring to the external terminals 115 situated on theinner side of the external terminal array increases in density as thepitch of the external terminals decreases making the on-board wiringmore difficult. Hence, the external terminals to be externallyinterconnected on the board are chosen as practically as possible fromamong those situated close to each other on the inner side.

[0105]FIG. 15 shows an example of on-board external connections betweenthose external terminals to which the signal terminals are output asshown in FIG. 14.

[0106] (Embodiment 4)

[0107] Implementing this invention also in the lead frame type MCM(Multi-Chip Module) configuration as shown in FIGS. 16a-16 c, i.e.,independently connecting the chips to the external terminals withoutinternally connecting them, can make the test environments of theindividual chips in the MCM package identical with the test environmentsoriginally developed for the individual chips., as described in theembodiment 1. FIG. 16a shows an example of module using a circuit board,FIG. 16b an example of a module using a lead frame, and FIG. 16c anexample of a module using a circuit board and a lead frame. Denoted 161is a first LSI chip, 162 a second LSI chip, 163 resin, 164 wires, 165lead frames, 166 thick film resistors, and 167 a chip capacitor.

[0108] (Embodiment 5)

[0109] The technical concept of this invention as exemplified in theembodiment 1 to embodiment 4 discussed above can similarly be applied toany package incorporating a plurality of chips.

[0110] For example, if there are demands for increasing the mountingdensity of “conventionally mounted” chips that are mounted on a motherboard or MCM circuit board as shown in FIG. 17 for a predeterminedfunction (they are assumed to be mounted either in the form of a packageor as bare chips) and if a large number of such products are expected tobe manufactured, then a plurality of chips may be grouped appropriatelyand incorporated into a single package. A three-dimensional chipmounting configuration is particularly effective in enhancing themounting density.

[0111] When incorporating a plurality of chips into one package, thisinvention is characterized in that the connections between the chips arenot brought into the package as practically as possible and that theterminals of each chip are drawn out of the package and individuallyconnected to external terminals. This arrangement ensures that theenvironment under which each of the chips mounted in a single package istested is very close to or identical with the environment under whicheach chip is tested as it is installed in its own package. This offers ahigh possibility that the existing test environment can be used as is,thus guaranteeing the test reliability. This also reduces the number oftest development processes required to develop a new package,contributing to a reduction in the development cost and developmentperiod.

[0112] If a part of the connections between a plurality of chips shouldbe accommodated in the package, the test reliability cannot beguaranteed unless some measures are taken to eliminate influences of thein-package chip-to-chip connections. An example case of accommodating apart of the connections between a plurality of chips into the packagemay be where it is required to shorten the interconnecting wire lengthsfor faster processing.

[0113] The present invention can be applied not only to the chips thatare closely related with each other and directly connected on the board(chip A and chip B in FIG. 17 in a closely related group) but also tothe chips which, though not directly connected, are deemed to constitutean indispensable combination to realize a certain function (chip D andchip E in a remotely related group). These applications are expected toproduce the similar effects.

[0114] In a package incorporating a group of the remotely related chips,because the in-package connections of one chip are independent of thoseof the other chips (power supply or ground may be shared), a failure ofone chip does not prevent the other normal chips from remainingoperational in the range of their functions.

[0115] (Embodiment 6)

[0116]FIG. 18 shows an example of package containing a combination of aDRAM as a memory and a controller that executes the image processing.

[0117] Further, FIG. 19 shows an example of package containing acombination of a DRAM and a flash memory. This type of package isexpected to have growing demands in the future in such applications ascellular phones that require a large capacity of temporary memory forimage communications.

[0118] In either of these packages the independent terminal arrangementaccording to this invention can be applied and the similar effects canbe expected to be produced.

[0119] (Embodiment 7)

[0120]FIG. 21 shows another example of the semiconductor disk device 100alternative to the embodiment 1, which is designed to facilitate thetesting of a plurality of chips accommodated in the semiconductorpackage 10. The semiconductor disk device 100 of the embodiment 7 has atest mode switching external terminal 17 formed in the semiconductorpackage 10 which receives a test mode switching signal from the externalcircuit. A plurality of chips 20, 30 in the semiconductor package 10 areinternally connected and connection selectors 61, 62 are provided atintersections between the internal buses 311 and 312 and between theinternal buses 313, 314 and 315.

[0121] When a test mode for the controller chip 30 is specifiedaccording to the test mode switching signal received from the externalcircuit, the selector 61 connects the controller chip 30 through theinternal bus 311 to the external terminal 12 and disconnects theinternal bus 312. At the same time, the selector 62 connects theinternal buses 313 and 314 to connect the controller chip 30 to theexternal terminal 18.

[0122] When a test mode for the memory chip 20 is specified, theselector 61 connects the internal bus 311 on the external terminal 12side to the internal bus 312 and disconnects the internal bus 311 on thecontroller side. The selector 62 connects the internal buses 314 and 315to connect the memory chip 20 to the external terminal 18 anddisconnects the internal bus 313.

[0123] With the test mode switched as described above, the controllerchip 30 or memory chip 20 can be tested independently by the test systemconnected to the external terminals 12, 18. This produces the similareffect to that obtained when the chips in the embodiment 1 are connectedindependently to the external terminals and tested.

[0124] When the semiconductor disk device 100 of this embodiment ismounted on the mother board, a normal mode signal is input to the testmode switching external terminal 17. Based on the input signal, theselector 61 connects the internal buses 311, 312 and the selector 62connects the internal buses 313, 314, 315. Then the controller chip 30can access the expansion memory 50 connected to the external terminals12, 18 in the same hierarchy as the built-in memory 20.

[0125] The connection selectors 61, 62 have a decoder to decode the testmode switching signal. The decoder has a built-in switch means tocontrol the internal bus, which is to be disconnected, at a high outputimpedance. The connection selectors 61, 62 may be taken as a tri-state(3-state) output circuit arranged in each output circuit of theplurality of chips 20, 30.

[0126] As to the location in the semiconductor package 10 where theconnection selectors 61, 62 are installed, they may be incorporated intothe input/output terminal blocks of the controller chip 30. As shown inFIG. 22, the connection selectors 63, 64 are incorporated in thecontroller chip 30, connected to the input/output terminal blocks(electrode pads) 33, 34. Although the input/output terminal blocks 33,34 are expected to have an increased number of electrode pads forconnection with external terminals and the memory chip 20, they offerthe advantage of being able to incorporate the connection selectors 63,64 in the controller chip 30. The functions of the connection selectors63, 64 are virtually the same as those of the connection selectors 61,62 of FIG. 21, except that the connection selectors 63, 64 switch theconnections to the internal circuits of the controller. The test modeswitching signal is commonly entered into the electrode pad 45 of thecontroller 30.

[0127] In the embodiment shown in FIG. 22, examples of possiblecombinations of the chip A 30 and chip B 20 are shown in Table 3. TABLE3 Chip A Chip B SRAM Flash SRAM DRAM Controller Flash Controller DRAM

[0128] The test mode switching signal terminal 22 shown in FIG. 21 andFIG. 22 need not be a dedicated external terminal but may not beprovided when the test mode switching signal is replaced with acombination of a plurality of other signals.

[0129] Provision of the connection selectors 61, 62, 63, 64 in thesemiconductor package 10 as described above allows the chips to beindividually tested under their own test environments in the same way asthey are tested in the semiconductor disk device 100 of theembodiment 1. The only difference is that the semiconductor disk device100 of this embodiment can accommodate in the semiconductor package 10the interconnecting wires 312, 313, 315 between a plurality of chips.

[0130] (Embodiment 8)

[0131]FIG. 23 shows a variation of the MCP type semiconductor diskdevice 100 explained in the embodiment 1 and 7. The semiconductor diskdevice 100 of this embodiment has internally connected between thecontroller 30 and the built-in memory 20 a signal path for a chip enablesignal CE1 by which the controller 30 selects and activates the built-inmemory 20. The controller 30 outputs through an external terminal 19chip enable signals CE2, CEn for selecting the expansion memories 51, 52mounted outside the semiconductor disk device 100. All otherinput/output signals necessary for the controller 30 to access thememory connect internally to the built-in memory 20 via the internal bus316. The internal bus 316 connects to the expansion memory interface 41so that the controller 30 can access the expansion memories 51, 52 viaan expansion memory bus 301. While in the embodiment of FIG. 23 allother input/output signals internally connect to the built-in memory 20through the internal bus 316, it is conceivable to have a part of thesesignals brought out to external terminals, through which the controller30 and the built-in memory 20 are externally connected as required, asshown in the embodiment 1 of FIG. 1.

[0132] The difference between this embodiment and JP-A-6-250799 as priorart is that this embodiment is a semiconductor disk device constructedin the MCP configuration while the prior art is a semiconductor diskdevice constructed on a one-chip LSI. Another difference is that theexpansion memory interface of this embodiment is the one thatmultiplexes address/data/command. If a part of the signals is broughtout to the external terminals through which the controller 30 and thebuilt-in memory 20 are externally connected as described above, theexpansion memory interface 41 becomes an interface common to theexpansion memories 51, 52 and the built-in memory 20. Thus, it isclearly different from the expansion memory interface of the prior artwhich is dedicated to only the expansion memory.

[0133] (Embodiment 9)

[0134]FIG. 24 shows an example configuration of a single semiconductordisk LSI 60 incorporating a controller unit 70 and a memory unit 80. Inthe testing of LSI of such a configuration, too, it is consideredappropriate to avoid the internal connection between the units aspracticably as possible in order to perform the test on the individualunits with high reliability. Hence, in the semiconductor disk LSI 60,the input/output blocks 73, 74, 81, 82 of the units 70, 80 areindependently connected to the external terminals 12, 13, 14, 15, 16 ofthe semiconductor package 10 sealing the LSI chip, as in theembodiment 1. After this semiconductor disk LSI has been mounted on theboard, the external terminals are connected on the board to form thesemiconductor disk device. The controller unit 70 accesses the memoryunit 80 through the external terminal (memory interface) 12, memory bus301 and external terminal 14.

[0135] The difference between this embodiment and JP-A-6-250799 as priorart is that the controller and the memory mounted on a single LSI inthis embodiment are not internally connected but externally connected onthe board through external terminals of the semiconductor package 10.Hence, the memory interface 12 is common to the built-in memory 80 andthe expansion memory and clearly differs from the interface of the priorart.

[0136] Rather than externally connecting all the signals between thecontroller unit 70 and the memory unit 80 as described above, only thosesignals whose internal connections between the units have largeinfluences on the testing of individual units may be externallyconnected through the external terminals, with the other signalsconnected internally.

[0137] Some of the embodiments of the present invention described abovemay be summarized as follows.

EXAMPLE 1

[0138] A semiconductor device including a first semiconductor chip and asecond semiconductor chip in a single package, the semiconductor devicecomprising:

[0139] a selector installed in a signal internal connecting portionbetween the first semiconductor chip, the second semiconductor chip andexternal terminals of the package to switch an internal connection;

[0140] a test mode input external terminal for inputting a test modesignal to the selector;

[0141] a first test mode in which the selector, according to the testmode signal, independently connects input/output terminals of the firstsemiconductor chip to the external terminals of the package anddisconnects the second semiconductor chip;

[0142] a second test mode in which the selector, according to the testmode signal, independently connects input/output terminals of the secondsemiconductor chip to the external terminals of the package anddisconnects the first semiconductor chip; and

[0143] a normal mode in which the selector, according to a normal modesignal, internally connects the first semiconductor chip and the secondsemiconductor chip.

EXAMPLE 2

[0144] A semiconductor device according to example 1, wherein theselector is incorporated in an input/output terminal portion of thefirst semiconductor chip, and internal connections are made between theinput/output terminals of the first semiconductor chip and theinput/output terminals of the second semiconductor chip and between theinput/output terminals of the first semiconductor chip and the externalterminals of the package.

EXAMPLE 3

[0145] A semiconductor device according to example 1 or 2, wherein thetest mode signal is replaced with a combination of a plurality of othersignals and the test mode input external terminal is replaced with aplurality of other signal input external terminals.

EXAMPLE 4

[0146] A semiconductor device including a first semiconductor chip and asecond semiconductor chip in a single package;

[0147] wherein signal electrode pads of the first semiconductor chip areconnected inside the package in a one-to-one relationship to firstexternal terminals of the package;

[0148] wherein signal electrode pads of the second semiconductor chipare connected inside the package in a one-to-one relationship to secondexternal terminals of the package;

[0149] wherein either a power supply terminal or a ground terminal iscommonly connected to the first semiconductor chip and the secondsemiconductor chip.

EXAMPLE 5

[0150] A semiconductor device according to example 1 or 4, wherein thefirst semiconductor chip is mounted on the second semiconductor chip,with a surface (back surface) of the first semiconductor chip oppositeits circuit forming surface securely bonded to a circuit forming surfaceof the second semiconductor chip, and a support lead of a lead frame issecurely bonded to the circuit forming surface of the secondsemiconductor chip and sealed with a resin.

EXAMPLE 6

[0151] A semiconductor device according to any one of examples 1 to 5,wherein, of the external terminals independently connected to theinput/output signal electrode pads of the first and second semiconductorchips, at least a pair of external terminals to be interconnected, oneconnected to the first semiconductor chip and one connected to thesecond semiconductor chip, is arranged so that these external terminalsare set close to each other.

EXAMPLE 7

[0152] A semiconductor device comprising:

[0153] a memory chip;

[0154] a host interface having a plurality of input/output externalterminals for connection with a host unit;

[0155] a controller chip to access-control the memory chip according toa memory access request received from the host unit through the hostinterface;

[0156] a plurality of first external terminals independently connectedto input/output terminals of the controller chip for the controller chipto access the memory; and

[0157] a plurality of second external terminals independently connectedto input/output terminals of the memory chip for the memory chip to beaccessed by the controller chip;

[0158] wherein the first external terminals and the second externalterminals are externally interconnected to allow the controller toaccess the memory.

EXAMPLE 8

[0159] A semiconductor device according to example 7, further includinga plurality of third external terminals to input and output an accesscontrol signal for the controller chip to access-control an expansionmemory connected outside the semiconductor device.

EXAMPLE 9

[0160] A semiconductor device according to example 7, wherein, of theexternal terminals connected to the address/data input/output electrodepads of the controller chip and the memory chip, at least a pair ofexternal terminals to be interconnected, one connected to the controllerchip and one connected to the memory chip, is arranged so that theseexternal terminals are set close to each other.

EXAMPLE 10

[0161] A semiconductor disk device comprising:

[0162] a semiconductor device mounted on a mother board, thesemiconductor device having:

[0163] a memory chip;

[0164] a host interface having a plurality of input/output externalterminals for connection with a host unit;

[0165] a controller chip to access-control the memory chip according toa memory access request received from the host unit through the hostinterface;

[0166] a plurality of first external terminals independently connectedto input/output terminals of the controller chip for the controller chipto access the memory; and

[0167] a plurality of second external terminals independently connectedto input/output terminals of the memory chip for the memory chip to beaccessed by the controller chip;

[0168] wherein the first external terminals and the second externalterminals are interconnected by wires on the mother board.

EXAMPLE 11

[0169] A semiconductor device comprising a control unit and a memoryunit in a single semiconductor chip;

[0170] wherein one signal output of the control unit and a firstexternal terminal of the semiconductor chip are independently andinternally interconnected;

[0171] wherein one signal input of the memory unit and a second externalterminal of the semiconductor chip are independently and internallyinterconnected;

[0172] wherein the first and second external terminals of thesemiconductor chip are interconnected outside the semiconductor chip tocomplete the connection between the signal output of the control unitand the signal input of the memory unit.

EXAMPLE 12

[0173] A semiconductor device having a control unit and a memory unitmounted in a single semiconductor chip;

[0174] wherein a path for inputting an output signal A of the controlunit into the memory chip comprises:

[0175] a first part path connecting an output portion of the controlunit and a first external terminal of the semiconductor chip;

[0176] a second part path connecting a second external terminal of thesemiconductor chip and an input portion of the memory chip; and

[0177] a third part path externally shortcircuit-connecting outside thesemiconductor chip the first external terminal and the second externalterminal of the semiconductor chip.

EXAMPLE 13

[0178] A semiconductor device according to example 11 or 12, wherein thecontrol unit has an interface function to respond to an access from ahost unit and an interface function to convert the access from the hostunit into an access unique to the memory unit and access-control thememory unit.

EXAMPLE 14

[0179] A semiconductor device according to any one of examples 1 to 3,wherein the first semiconductor chip is an SRAM or a controller and thesecond semiconductor chip is a flash memory (block erase type EEPROM) ora DRAM.

EXAMPLE 15

[0180] A semiconductor device according to example 4, wherein wheneither the first or second semiconductor chip fails during a test, thefailed semiconductor chip is taken out of service and only the remainingsemiconductor chip is allowed to operate.

EXAMPLE 16

[0181] A semiconductor disk device comprising:

[0182] a semiconductor device having accommodated in a single package amemory chip, a host interface having a plurality of input/outputexternal terminals for connection with a host unit, a controller chip toaccess-control the memory chip according to a memory access requestreceived from the host unit through the host interface, and a memoryinterface having a plurality of input/output external terminals for thecontroller chip to access an external expansion memory;

[0183] a mother board on which to mount the semiconductor device; and

[0184] an expansion memory connected to the memory interface of thesemiconductor device.

EXAMPLE 17

[0185] A semiconductor disk device according to example 16, wherein thesemiconductor device has a package structure in which the memory chipand the controller chip are stacked and sealed with resin.

EXAMPLE 18

[0186] A semiconductor disk device according to example 16, wherein theexpansion memory is in the form of a package mounted on the motherboard, the package incorporating a plurality of memory chips stacked andsealed with resin.

[0187] As explained in the above example embodiments, a plurality ofkinds of semiconductor chips are accommodated in a single package toreduce the mounting area. Further, the internal connection among thechips inside the package is precluded as practically as possible and theterminals (electrode pads) of the chips are independently connected tothe external terminals of the package. When the chips in the package aretested, this arrangement eliminates influences of signals from otherchips than the one being tested and influences of leakage currents. Itis therefore possible to provide an environment under which theindividual chips can be tested independently. As a result, the existingtest system which was originally developed for the individual chiptesting can be used as is or with only a slight modification. Hence,performing the test on the chips individually can guarantee thereliability of the test. This in turn eliminates the need to develop anew test system, keeping the product development TAT and cost low.

[0188] As a variation of this invention, it is possible to provide atest selector in the package and to select a desired internal connectionaccording to a mode signal to test the chips independently. In this testmethod, too, the test system originally developed for the individualchip testing can be used with the similar effects. In this case,however, the selector needs to be installed on the internal wires insidethe package, or in the controller chip.

1. A semiconductor device comprising: a memory chip; a first interfacehaving a plurality of input/output external terminals for connectionwith a host unit; and a controller chip having a function to respond toa memory access request received from the host unit through the firstinterface and a function to convert the memory access request into anaccess unique to the memory chip and access-control the memory chip;wherein the memory chip, the first interface and the controller chip arecontained in a single package; wherein a signal interface for thecontroller chip to access the memory chip is provided to a plurality offirst external terminals of the package and a signal interface for thememory chip to be accessed is provided to a plurality of second externalterminals of the package.
 2. A semiconductor device according to claim1, wherein the memory chip is a flash memory chip.
 3. A semiconductordevice according to claim 1, wherein the memory chip is a DRAM chip oran SRAM chip.
 4. A semiconductor device according to claim 1, whereinthe controller chip further includes a function to write data into thememory chip by adding an error correction code to the data and torecover the data from the memory chip by performing error correctionprocessing on the data read from the memory chip.
 5. A semiconductordevice according to claim 1, wherein the controller chip furtherincludes a function to write data requiring security into the memorychip by performing encryption processing on the data and to performdecryption processing on the data read from the memory chip.
 6. Asemiconductor device comprising: a first semiconductor chip, a secondsemiconductor chip and a support lead, all stacked and bonded togetherwith an insulating adhesive layer therebetween; a plurality of leadsarranged around outer peripheral sides of the first and secondsemiconductor chips, each of the leads having an inner portion and anouter portion, the inner portions being electrically connected throughconductive wires to electrode pads of the first and second semiconductorchips; and a resin sealing body sealing the first and secondsemiconductor chips, the wires and the inner portions of the leads;wherein an output signal A from the first or second semiconductor chipis output to a first external terminal of the semiconductor device, anda second external terminal of the semiconductor device as an inputterminal of the signal A is connected to the electrode pad of the othersemiconductor chip.
 7. A semiconductor device according to claim 6,wherein the first semiconductor chip is a controller chip and the secondsemiconductor chip is a memory chip.
 8. A semiconductor device accordingto claim 7, wherein the controller chip has an interface function torespond to an access from the host unit and an interface function toconvert the access from the host unit into an access unique to thememory chip and thereby access-control the memory chip.
 9. Asemiconductor device according to claim 6, wherein the signal electrodepads of the first semiconductor chip and the second semiconductor chipare connected inside the package in a one-to-one relationship to theexternal terminals of the package; wherein the first external terminalof the package that outputs an output signal A from one of the first andsecond semiconductor chip and the second external terminal of thepackage that inputs the signal A and is connected to the electrode padof the other semiconductor chip are arranged close to each other in thepackage.
 10. A semiconductor device comprising: a first semiconductorchip and a second semiconductor chip, both mounted on an upper surfaceor lower surface of a circuit board or a support lead; a plurality ofleads arranged around outer peripheral sides of the first and secondsemiconductor chips, each of the leads having an inner portion and anouter portion, the inner portions being electrically connected throughconductive wires to electrode pads of the first and second semiconductorchips; and a resin sealing body sealing the first and secondsemiconductor chips, the wires and the inner portions of the leads;wherein an output signal A from the first or second semiconductor chipis output to a first external terminal of the semiconductor device, anda second external terminal of the semiconductor device as an inputterminal of the signal A is connected to the electrode pad of the othersemiconductor chip.
 11. A semiconductor device according to claim 10,wherein the first semiconductor chip is a controller chip and the secondsemiconductor chip is a memory chip.
 12. A semiconductor deviceaccording to claim 11, wherein the controller chip has an interfacefunction to respond to an access from the host unit and an interfacefunction to convert the access from the host unit into an access uniqueto the memory chip and thereby access-control the memory chip.
 13. Asemiconductor device according to claim 10, wherein the signal electrodepads of the first semiconductor chip and the second semiconductor chipare connected inside the package in a one-to-one relationship to theexternal terminals of the package; wherein the first external terminalof the package that outputs an output signal A from one of the first andsecond semiconductor chip and the second external terminal of thepackage that inputs the signal A and is connected to the electrode padof the other semiconductor chip are arranged close to each other in thepackage.